Introduction

Dr. Dilip Singh received his B.Tech. in Electronics & Communication Engineering from Uttar Pradesh Technical University, Lucknow, India in 2016. He did his M.Tech. Degree in VLSI Design from the National Institute of Technology (NIT) Hamirpur in 2018. He was awarded a Ph.D. Degree in Electronics & Communication Engineering from NIT Hamirpur in 2024. He completed Post-Doc at IIT Madras in 2025. Presently, Dr. Dilip Singh is working as an Assistant Professor in the Electronics & Communication Engineering Department at IIIT Senaptati Manipur. He is the author/co-author of reputed publications in Journals and Conference proceedings of repute. His major research interests are in hardware acceleration, VLSI design, Speech coding, and FPGA-based system design.

Qualification

  • Ph.D. in Electronics & Communication Engineering — NIT Hamirpur (2024)
  • M.Tech. in Electronics & Communication Engineering — NIT Hamirpur (2018)
  • B.Tech. in Electronics & Communication Engineering — Dr APJ Abdul Kalam Technical University Lucknow (2016)

Experience

  • Assisatnt Professor — IIIT Manipur (2025–Present). Academic, research and Administrative responsibility.
  • Post Doctoral Fellow — IIT Madras (2024–2025). Research and development

Publications

  1. Dilip Singh and Rajeevan Chandel, “An Efficient FPGA-Based Accelerator for Perceptual Weighting Filter in Speech Coding,” IETE Technical Review, vol. 41(4), pp. 441-453 (2023). link
  2. Dilip Singh and Rajeevan Chandel, “FPGA-Based Hardware-Accelerated Design of Linear Prediction Analysis for Real-Time Speech Signal,” Arab J Sci Eng, vol. 48, pp. 14927-14941 (2023). link
  3. Dilip Singh and Rajeevan Chandel, “An FPGA Implementation of the Levinson-Durbin Algorithm for Speech Coding,” 3rd International Conference on Computational Electronics for Wireless Communications, Dr. B. R. Ambedkar National Institute of Technology Jalandhar, India, vol 959. Springer, Singapore (2025). link
  4. B. K. Jangid, D. Singh, R. Chandel and A. Rana, "A Novel Approach for Excitation Codebook and Perceptual Weighting Filter Design," 2021 Innovations in Power and Advanced Computing Technologies (i-PACT), Kuala Lumpur, Malaysia, 2021, pp. 1-6. link
  5. P.K. Pandey, D. Singh, R. Chandel, “Fixed-Point Divider Using Newton Raphson Division Algorithm,” In: Nath, V., Mandal, J.K. (eds) Proceeding of Fifth International Conference on Microelectronics, Computing and Communication Systems. Lecture Notes in Electrical Engineering, vol 748. Springer, Singapore, 2021. link
  6. Singh, R. Chandel, “Register-Transfer-Level Design for Application-Specific Integrated Circuits,” In: Dhiman, R., Chandel, R. (eds) Nanoscale VLSI. Energy Systems in Electrical Engineering. Springer, Singapore, 2020. link

Referee

  1. Reviewer - MNDCS 2025
  2. Reviewer - EAIC 2025